Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, placement, and routing. When designing large systems to be implemented on large target devices, EDA tools may require a large amount of time to perform these compilation procedures.
Although the design process is automated with EDA tools, generating a satisfactory system design may still be time consuming. It is an ongoing effort for EDA tool designers to shorten the runtime of its algorithms. By shortening the runtime of its algorithms, more flexibility may be offered to the system designer using the EDA tool and/or additional algorithms may be implemented in the EDA tool in order to further improve a system design.
In FPGA design, system designs are very structured in nature. It is not uncommon for a system design to include a plurality of subnetworks (subnets) that have common characteristics. Current EDA tools execute algorithms on a subnet regardless of whether an identical subnet had been previously processed. For system designs that include a large number of subnets having identical characteristics, this results in the consumption of a significant amount of time and computing resources for repetitive computations.